Field of the Invention
The present invention relates to an analog/digital converter and a solid-state imaging device.
Description of the Related Art
In recent years, a complementary metal oxide semiconductor (CMOS) image sensor has gathered attention as a solid-state imaging device and has been practically used. The CMOS image sensor can be manufactured using an ordinary semiconductor manufacturing process, whereas a charge coupled device (CCD) image sensor is manufactured using a dedicated manufacturing process. Thus, a multi-functional CMOS image sensor can be realized by incorporating various functional circuits in the sensor, for example, as a system-on chip (SOC).
In recent years, there is an increasing number of examples of a solid-state imaging device including an analog/digital converter (hereinafter referred to as an “A/D conversion circuit”) as a solid-state imaging device mounted on a digital camera, a digital video camera, or an endoscope. A single-slope A/D conversion circuit which uses ramp waves is used as an A/D conversion circuit included in such a solid-state imaging device. The single-slope A/D conversion circuit is provided in each column of a solid-state imaging device to form a single-slope column A/D conversion circuit (for example, see Japanese Patent No. 4655500). In the following description, an A/D conversion circuit is assumed to indicate a single-slope A/D conversion circuit.
FIG. 9 is a block diagram showing a schematic configuration of a conventional solid-state imaging device. A conventional solid-state imaging device 600 shown in FIG. 9 includes a vertical scanning circuit 601, a pixel array portion 602, an analog signal processing circuit 603, a ramp signal generation circuit (hereinafter referred to as “DAC”) 604, a column A/D conversion circuit 605, a horizontal scanning circuit 606, and a control circuit 607.
The solid-state imaging device 600 removes noise from pixel signals output from respective pixels 61 in the pixel array portion 602, converts analog signals Vin obtained after the noise removal to digital signals Dout with the aid of A/D conversion circuits 609 provided in the column A/D conversion circuit 605, and sequentially outputs the digital signals Dout.
The vertical scanning circuit 601 selects the pixels 61 in the pixel array portion 602 disposed in each row of the pixel array portion 602 respectively according to a control signal input from the control circuit 607 and outputs pixel signals generated by the respective pixels 61 of the selected row to the analog signal processing circuit 603. In the following description, a period of time from a certain row of the pixel array portion 602 being selected to the next row being selected is referred to as a “horizontal period”.
The pixel array portion 602 is a pixel array in which a plurality of pixels 61 are disposed 2-dimensionally in row and column directions. Each of the pixels 61 includes a photodiode, and the photodiode provided in the pixel 61 generates a pixel signal corresponding to the amount of light which is incident in a certain storage period. The pixel array portion 602 outputs a pixel signal generated by the selected pixel 61 to the analog signal processing circuit 603 according to the selection from the vertical scanning circuit 601.
The analog signal processing circuit 603 removes reset noise and 1/f noise from the pixel signal input from the pixel array portion 602 according to the control signal input from the control circuit 607 and amplifies the pixel signal obtained after the noise removal. The analog signal processing circuit 603 outputs the amplified pixel signal to the column A/D conversion circuit 605 as the analog signal Vin.
The DAC 604 generates a ramp wave Vramp, which is an analog signal of which the potential decreases with time at a certain rate in each horizontal period according to the control signal input from the control circuit 607, and outputs the generated ramp wave Vramp to the column A/D conversion circuit 605.
The control circuit 607 outputs a control signal configured to control the driving of the vertical scanning circuit 601, the analog signal processing circuit 603, the DAC 604, and the horizontal scanning circuit 606.
The column A/D conversion circuit 605 includes a number of A/D conversion circuits 609 corresponding to the number of columns of the pixels 61 disposed in the pixel array portion 602 each of the A/D conversion circuits 609 has the same configuration, which includes a comparator 62 and a data processing circuit 63 including a counter, a memory, and the like.
In the A/D conversion circuit 609 corresponding to each column of the pixel array portion 602, the comparator 62 performs a process (hereinafter referred to as a “comparison process”) of comparing a potential of the input analog signal Vin and the potential of the ramp wave Vramp in each horizontal period. Moreover, in each A/D conversion circuit 609, the counter in the data processing circuit 63 counts the time (counts the number of clock cycles) from a time of an initial value of the ramp wave Vramp to a time of a completion of a comparison process of the comparator 62. Further, each A/D conversion circuit 609 outputs a digital signal indicating the time counted by the counter in the data processing circuit 63 as a digital signal Dout generated according to the magnitude of the analog signal Vin input to the A/D conversion circuit 609.
The horizontal scanning circuit 606 selects the digital signal Dout converted by each A/D conversion circuit 609 provided in the column A/D conversion circuit 605 in respective columns of the pixel array portion 602 according to the control signal input from the control circuit 607 and sequentially outputs the digital signal Dout of the selected column as the output of the solid-state imaging device 600.
In this manner, the conventional solid-state imaging device 600 outputs the digital signal Dout obtained by the column A/D conversion circuit 605 converting the analog signal Vin obtained after removing noise from the pixel signal generated by each pixel 61 of the pixel array portion 602.
Here, the operation of the A/D conversion circuit 609 provided in the conventional solid-state imaging device 600 will be described. FIG. 10 is a timing chart showing the operation of the A/D conversion circuit 609 provided in the conventional solid-state imaging device 600. FIG. 10 shows waveforms of the analog signal Vin and the ramp wave Vramp input to the comparator 62 provided in the A/D conversion circuit 609 in one horizontal period of the solid-state imaging device 600 and a comparator output signal CMPOUT output as a result of the comparison process of the comparator 62.
In an analog/digital conversion operation of the A/D conversion circuit 609, the comparator 62 provided in the A/D conversion circuit 609 compares the potential of the input analog signal Vin and the potential of the ramp wave Vramp in a reset period and a signal read period. More specifically, the comparator 62 compares the analog signal Vin with a reset level in the reset period and compares the analog signal Vin with a signal level in the signal read period. As shown in FIG. 10, the comparator 62 outputs the comparator output signal CMPOUT when the potential of the ramp wave Vramp is equal to or lower than the potential of the analog signal Vin in the respective periods.
In this case, the data processing circuit 63 provided in the A/D conversion circuit 609 counts the time (counts the number of clock cycles) from the time of the initial value ramp wave Vramp to a time at which the comparator output signal CMPOUT is output from the comparator 62 in each of the reset period and the signal read period. More specifically, the counter in the data processing circuit 63 counts the time (counts the number of clock cycles) of a period tr shown in FIG. 10, from the time of the initial value of the ramp wave Vramp to the time at which the comparison process of the comparator 62 is completed in the reset period. In this way, as shown in FIG. 10, a digital signal (that is, digital value Dr) corresponding to the magnitude (that is, the value of a reset signal of the pixel 61) of the reset level of the analog signal Vin is obtained. Moreover, the counter in the data processing circuit 63 counts the time (counts the number of clock cycles) of a period ts shown in FIG. 10, from the time of the initial value of the ramp wave Vramp to the time at which the comparison process of the comparator 62 is completed in the signal read period. In this way, as shown in FIG. 10, a digital signal (that is, digital value Dr+digital value Ds) corresponding to the magnitude (that is, the sum of the values of the reset signal and the pixel signal of the pixel 61) in which the reset level and the signal level of the analog signal Vin are combined is obtained.
The data processing circuit 63 outputs a digital signal Dout corresponding to the magnitude of the analog signal Vin input to the A/D conversion circuit 609 based on the digital signal indicating the time (the number of clock cycles) counted by the counter in the reset period and the signal read period. More specifically, the data processing circuit 63 performs a digital correlated double sampling (CDS) process of subtracting the digital signal (that is, digital value Dr) obtained in the reset period from the digital signal (that is, digital value Dr+digital value Ds) obtained in the signal read period and outputs a digital signal Dout having the value (that is, digital value Ds) of a pixel signal corresponding to the amount of light incident on the pixel 61.
In this manner, in the conventional solid-state imaging device 600, the counter in the data processing circuit 63 provided in each A/D conversion circuit 609 disposed in each column counts the time (counts the number of clock cycles) elapsed from the time of the initial value of the ramp wave Vramp to the time at which the comparison process of the comparator 62 is completed in each horizontal period, whereby the digital signal Dout having the value (that is, digital value Ds) of the pixel signal corresponding to the amount of light incident on the pixel 61 is output.